1 Synthesis results

Table 2: Implementation results for architectures 1,2 and 3.

	Processor	Slices	BRAM
	MicroBlaze	1321 (6%)	74 (46%)
	LEON	4883 (25%)	43 (26%)
	LEON+Meiko FPU	6064 (31%)	40 (25%)

The results are shown in table 2. Since MicroBlaze processor is highly optimized for Xilinx FPGA circuit the resources used are lower than for the LEON2 processor. LEON2 is written not only for FPGA circuit so it is very difficult for a synthesis tool to synthesize LEON2 with the same low FPGA resource optimization as MicroBlaze. Also, as can be seen in table 1 the maximum clock frequency achieved for MicroBlaze is 50Mhz, whereas LEON2 runs at 25Mhz in the selected FPGA device.

The improved architecture LEON2 with FPU unit only suppose a 6% of additional resources