2 Implementation results

The implementation of the controlling system has been developed using the latest released Xilinx software for HDL synthesis, mapping and implementation, ISE 6.1. And the processor system developer tool, also from Xilinx EDK 6.1. The FPGA used in Cube is a SpartanIIE 400, a low cost FPGA that maintains the objective of a low cost robot. The obtained results for the final place and route of the hardware system are shown in table .

Table: Implementations results using an SpartanIIE 400 FPGA

	Total	Used	Available BRAMs
BRAMS	14	8	6(43%)
Slices (Area)	2352	1312	1040 (44%)
I/O Pins	146	10	136 (93%)
System Clock frequency (MHZ)	--	50	--

The 8 BRAM are configured to build a 32 bit words memory, having each BRAM a 4Kx4 bit capacity sharing the address bus. The results obtained for the controller leave a 44% of space and 93% of the pins free in the FPGA. So that, the system still has a remarkable amount of resources available for future improvements. The board uses a 50 MHz clock generator, even considering that no optimization of the design has been carried out.

The average robot power comsuption depends on the movement performed and will be analized in detail in future work. A Typical value is 8W (1.6A, 5v).